李华伟，女，汉族，毕业于中国科学院计算技术研究所，现任计算机体系结构国家重点实验室研究员、博士生导师。2022年6月，李华伟任中国科学院计算技术研究所处理器芯片全国重点实验室副主任、研究员。

2021年12月27日，李华伟当选为2021年度中国计算机学会会士。

2001年7月至今就职于中国科学院计算技术研究所，现为计算机体系结构国家重点实验室研究员、博士生导师。

2016-01-01-至今，中国计算机学会容错计算专委会，主任。

2016-01-01-至今，中国计算机学会，理事。

2014-12-31-2018-12-31,IEEE TVLSI期刊编委,Associate Editor。

2014-01-01-至今,《计算机研究与发展》编委。

2010-01-01-至今,《计算机辅助设计与图形学学报》编委。

2009-08-2010-08月，美国UCSB大学电子与计算机工程系任访问教授。

2007-12-30-2015-12-31,中国计算机学会容错专业委员会，秘书长。

2019-10-16-今,中国计算机学会集成电路设计专业组,秘书长

2018-08-14-今,中国计量测试学会集成电路测试专业委员会,副主任兼秘书长

2016-12-31-2017-12-30,第十七届全国容错计算学术会议,大会主席

2016-01-01-2019-12-31,中国计算机学会容错计算专业委员会,主任

2015-12-30-2019-12-31,中国计算机学会,理事

2014-01-01-今,《计算机研究与发展》,编委

2010-01-01-今,《计算机辅助设计与图形学学报》,编委

2007-12-29-2015-12-30,中国计算机学会容错计算专业委员会,秘书长

项目

主要从事VLSI测试、可靠设计、验证、容错计算领域的应用基础研究工作。主持的主要国家项目如下：

1、国家自然科学基金重点项目，差错容忍计算器件基础理论与方法，2015/01-2019/12。

2、国家自然科学基金面上项目，考虑集成电路时延变异性的硅后定时验证方法，2012/01-2015/12。

3、国家自然科学基金面上项目，避免过度测试的时延测试方法，2008/01-2010/12。

4、国家重点基础研究发展计划（973计划）项目，高性能处理芯片的设计验证与测试，2005/12–2010/12。

5、国家高技术研究发展计划（863计划）项目，可信计算平台软硬件系统安全测试评估模型、测试方法以及测试自动化技术，2007/07–2009/12。

6、国家自然科学基金面上项目，面向串扰的时延测试，2007/01-2009/12。

论文

Ying Wang, Yinhe Han, Cheng Wang, 华为 Li, Xiaowei Li, “Retention-Aware DRAM Assembly and Repair for Future FGR Memories”, IEEE Transaction on Computer Aided 设计 of Integrated Circuits and Systems (TCAD), Vol. 36, No.5, pp.705-718, 2017.

Jian Wang, 华为 Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE Transaction on 计算机 Aided 设计 of Integrated Circuits and Systems (TCAD), Vol. 35, 二氧化氮, pp.285-297, 2016.

Yanhong Zhou, Tiancheng Wang, 华为 Li, Tao Lv, Xiaowei Li, “Functional Test Generation for Hard-to-reach States Using Path Constraint Solving,” IEEE Transaction on 计算机 Aided 设计 of Integrated Circuits and Systems (TCAD), Vol. 35, No.6, pp.999-1011, 2016.

Guihai Yan, Faqiang Sun, 华为 Li, Xiaowei Li, “CoreRank: Redeeming Imperfect 硅 by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors”, IEEE Transactions on Computers, Vol. 65, No.3, pp.716-729, 2016.

Yun Cheng, 华为 Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “Flip-flop Clustering based Trace Signal Selection for Post-硅 Debug,” Proc. of IEEE VLSI Test Symposium (VTS’17), Paper 3A-2, USA, April 2017.

Ying Wang, 华为 Li, Xiaowei Li, “Re-architecting the On-chip memory Sub-system of Machine-Learning Accelerator for Embedded Devices,” Prof. of IEEE International Conference On 计算机 Aided 设计, USA, Nov. 2016.

Ying Wang, Jie Xu, Yinhe Han, 华为 Li, Xiaowei Li, “DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family”, IEEE/ACM Proceedings of 设计, Automation Conference (DAC), USA, 2016.

Ying Wang, Yinhe Han, Jun Zhou, 华为 Li, Xiaowei Li, “DISCO: A Low Overhead In-Network 数据 Compressor for 能量Efficient Chip Multi-Processors”, IEEE/ACM Proceedings of 设计, 自动化技术 Conference (DAC), USA, 2016.

Huina Chao, 华为 Li, Tiancheng Wang, Xiaowei Li and Bo Liu, “An accurate algorithm for computing mutation coverage in model checking,” Prof. IEEE International Test Conference, USA, Paper 16.2, Nov. 2016.

Yanhong Zhou, 华为 Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li, “Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage,”, Proc. of IEEE VLSI Test Symposium (VTS’16), Paper 1B-2, USA, April 2016.

Ying Wang, Yinhe Han, 华为 Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li, “PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3D Die-Stacked PCM”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol.24, No.5, pp.1613-1625, 2016.

Ying Wang, Lei Zhang, Yinhe Han, 华为 Li, Xiaowei Li, “数据 Remapping for Static NUCA in Degradable Chip Multiprocessors”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.5, pp. 879-892, 2015.

Ying Wang, Lei Zhang, Yinhe Han, 华为 Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip 设计”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.3, pp. 493-506, 2015.

Dawen Xu, Huawei Li, Amirali Ghofrani, KT Rolster Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.8, pp. 1738-1749, August 2014.

Binzhang Fu, Yinhe Han, 华为 Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant 路由 for 2D Meshes Without Virtual Channels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.1, pp.113-126, 2014.

Yuntan Fang, 华为 Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.6, pp. 1450-1455, June 2014.

Song Jin, Yinhe Han, 华为 Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.5, May 2013, pp.821-833.

Ying Zhang, 华为 Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1220-1233.

Zijian He, Tao Lv, 华为 Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1210-1219.

Yuntan Fang, 华为 Li, Xiaowei Li, “RSAK: Random Stream AttacK for Phase Change Memory in Video Applications,” Proc. of IEEE VLSI Test Symposium (VTS’13), Paper 10B-3, Berkeley, CA, USA, May 2013.

Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, 二氧化氮, 2012, pp.236-247.

Songwei Pei, 华为 Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test 数据 Volume,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.12, 2012, pp. 2157-2169.

Songwei Pei, 华为 Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement 建筑,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.9, 2012, pp.1565-1577.

Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition 时间 Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.10, 2011, pp.1787-1800.

Minjin Zhang, 华为 Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.11, 2011, pp.1969-1982.

Songwei Pei, 华为 Li, and Xiaowei Li, “A Unified Test 建筑 for on-Line and Off-Line Delay Fault Detections", Proc. IEEE VLSI Test Symposium (VTS’11), 2011, pp.272-277.

[27]Huawei Li, Dawen Xu, K.-T. Cheng, “GPU-accelerated fault simulation and its new applications,” Proc. 2011 International Symposium on VLSI 设计, Automation and Test (V LSI-DAT), invited paper in Special Session I (GPU Applications), Taiwan, April 2011.

华为 Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,”Proc. IEEE 41st International Test Conference (ITC’10), Paper 12.1, Austin, USA, Oct. 2010.

Zijian He, Tao Lv, 华为 Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path correlations,” Proc. of IEEE 28th VLSI Test Symposium (VTS’10), Santa Cruz, USA, May 2010, pp.3-8.

Songwei Pei, 华为 Li, Xiaowei Li, “An On-Chip Clock Generation Scheme for Faster than-at-Speed Delay Testing”, Proc. of 设计 自动化技术 and Test in Europe (DATE’10), France, Mar. 2010, pp.1353-1356.

Huawei Li, Peifu Shen, and Xiaowei Li, “Robust Test Generation for Crosstalk-Induced Path Delay Faults,” 24th IEEE VLSI Test Symposium (VTS’06), Berkeley, CA, USA, May 2006.

华为 Li, and Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test,”Journal of Electronic Testing: Theory and Applications, Vol. 21, 二氧化氮, 2005, pp.181-195.

[33]Huawei Li, Yue Zhang, and Xiaowei Li, “Delay Test Pattern Generation Considering Crosstalk-induced Effects,” IEEE 12th Asian Test Symposium (ATS’03), Xi’an, China, Nov. 2003, pp.178-183.

华为 Li, Zhongcheng Li, and Yinghua Min, “Reduction of Number of Paths to be tested in Delay Testing,”Journal of Electronic Testing: Theory and Applications, Vol.16, No.5, Oct. 2000, pp. 477-485.

研究领域

集成电路设计自动化、近似计算、容错计算、设计验证与测试。

VLSI测试与可测试性设计

VLSI测试与可测性设计

数字电路的故障诊断与可靠设计

数字系统的故障诊断与容错设计

参考资料：

李华伟在微处理器全生命周期可靠设计和专用处理器自动设计的研究与应用方面取得了重要成绩，CCF学术服务贡献突出。（中国计算机学会夏培肃奖会士评选委员会评）